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Introduce CH32V203 and WeactStudio CH32V203 Blue Pill plus #87490

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@VynDragon VynDragon commented Mar 21, 2025

Introduces CH32V203 and WeactStudio CH32V203 Blue Pill +

DNM until #87125 and associated fixes and changes are merged.

Introduces the Soc for ch32v203

Signed-off-by: Camille BAUD <[email protected]>
Introduce CH32V203 SoC

Signed-off-by: Camille BAUD <[email protected]>
Adds CH32V203 support

Signed-off-by: Camille BAUD <[email protected]>
Adds CH32V203 to the systick timer driver

Signed-off-by: Camille BAUD <[email protected]>
@VynDragon VynDragon force-pushed the CH32V203 branch 2 times, most recently from 275509a to c9b2d89 Compare March 21, 2025 18:33
@VynDragon VynDragon marked this pull request as ready for review March 21, 2025 19:52
@zephyrbot zephyrbot added area: Timer Timer area: RISCV RISCV Architecture (32-bit & 64-bit) labels Mar 21, 2025
kartben
kartben previously approved these changes Mar 23, 2025
drive-push-pull;
slew-rate = "max-speed-10mhz";
};
group2 {
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newline

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Done

Programming and Debugging
*************************

Applications for the ``bluepillplus_ch32v203`` board target can be built and flashed
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Suggested change
Applications for the ``bluepillplus_ch32v203`` board target can be built and flashed
Applications for the ``bluepillplus_ch32v203`` board can be built and flashed

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Done

@VynDragon VynDragon added the DNM This PR should not be merged (Do Not Merge) label Mar 24, 2025
Introduces WeActStudio Blue Pill Plus CH32V203

Signed-off-by: Camille BAUD <[email protected]>
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LGTM, just some nits.


* CLOCK
* :abbr:`GPIO (General Purpose Input Output)`
* :abbr:`NVIC (Nested Vectored Interrupt Controller)`
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And the UART?

* :abbr:`GPIO (General Purpose Input Output)`
* :abbr:`NVIC (Nested Vectored Interrupt Controller)`

The board is equipped with two LEDs and two Buttons.
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nit: it's two LEDs, but only one is controllable, and 3 buttons.

Perhaps say "with a user LED and user button in addition to a power LED, reset button, and boot select button."

also s/Button/button/

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I forgot to update that part, thats from linkw.


flash0: flash@8000000 {
compatible = "soc-nv-flash";
reg = <0x08000000 DT_SIZE_K(224)>;
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64 K?

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@VynDragon VynDragon Apr 7, 2025

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Nope, 224K. 64K is the zerowait, CH32V203 has 224K flash,and it's enabled in here (see Vector.S)

config SYS_CLOCK_HW_CYCLES_PER_SEC
default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)

config MAIN_STACK_SIZE
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You can probably drop these. They were added for the CH32V003 as it has 2 KiB of RAM.

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@VynDragon VynDragon Apr 7, 2025

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I have to update that part anyway, this is awaiting the merge of a couple other things and i havent bothered updating the pr (#87345), this is why this is DNM

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area: RISCV RISCV Architecture (32-bit & 64-bit) area: Timer Timer DNM This PR should not be merged (Do Not Merge)
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